1. Field of the Invention
The present invention relates in general to a level shifting circuit. In particular, the present invention relates to a level shifting circuit for metal-oxide-semiconductor (MOS) transistors with relatively high threshold voltage.
2. Description of the Related Art
Level shifting circuits adjust the input voltage level for specific units. FIG. 1 shows a circuit diagram of a conventional level shifting circuit. The conventional level shifting circuit controls a NMOS transistor by a complementary pair of small signals Vin and XVin to lower the small signal with lower level to VSS or raise the small signal with higher level to VDD.
The conventional level shifting circuit comprises PMOS transistors P1 and P1xe2x80x2, whose sources are coupled to a first power source (9V as an example) with gates coupled to each other""s drains, wherein the connection points are labels 10 and 12. The drains of the NMOS transistors N1 and N1xe2x80x2 are coupled to the connection points 10 and 12. The sources of the NMOS transistors N1 and N1xe2x80x2 are coupled to VSS, and the gates of the NMOS transistors N1 and N1xe2x80x2 are controlled by the input signals Vin and XVin, respectively. Here, the voltage level of XVin is reversed to Vin. When Vin is at high level (3.3V as an example), XVin is at low level (0V as an example). Therefore, NMOS transistor N1 is turned on and lowers the voltage level of the connection point 10 to VSS. Thus, the PMOS P1xe2x80x2 is turned on. Since the NMOS transistor N1xe2x80x2 is turned off, the signal output from output terminal Vout is VDD. On the contrary, when Vin is at low level, XVin is at high level (3.3V). Therefore, NMOS transistor N1xe2x80x2 is turned on and lowers the voltage level of the connection point 12 to VSS. Thus, the signal output from output terminal Vout is VSS.
To increase voltage lowering rate of the connection points 10 and 12, NMOS transistors N2 and N2xe2x80x2 are added. The gates of the NMOS transistors N2 and N2xe2x80x2 are coupled to VCC, 3.3V as an example. Thus, the NMOS transistors N2 and N2xe2x80x2 are turned on. Therefore, the voltage lowering rate of the connection points 10 and 12 is increased when the NMOS transistors N1 or N1xe2x80x2 are turned on. Thus, the operating rate of the level shifting circuit is increased, and the timing error is prevented.
However, the conventional level shifting circuit described above is not suited to circuits based on low temperature poly silicon (LTPS hereinafter). The threshold voltage of the LTPS MOS transistor is around 2.5V. Thus, the NMOS transistors N2 and N2xe2x80x2 in FIG. 1 cannot be well turned on. Therefore, the conventional level shifting circuits meet serious RC delay in high operation frequency when applied to LTPS field.
The object of the present invention is to provide a level shifting circuit to ensure high level input signal transforming to VDD and the low level input signal transforming to VSS even when the voltage level of the input signal is swimming.
To achieve the above-mentioned object, the level shifting circuit of the present invention includes a PMOS transistor, a NMOS transistor, and a reverse logic gate. The gate of the PMOS transistor is coupled to an input terminal, and the source of the PMOS transistor is coupled to a power source. The drain of the NMOS transistor is coupled to the drain of the PMOS transistor. The source of the NMOS transistor is coupled to a reverse input terminal. The gate of the NMOS transistor is coupled to the power source. The reverse logic gate, having a first terminal is coupled to the drain of the NMOS transistor and a second terminal is coupled to the output terminal.
Moreover, the level shifting circuit of the present invention includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor and a second NMOS transistor. The first PMOS transistor comprises a first drain, a first gate coupled to an input terminal, and a first source coupled to a power source. The first NMOS transistor comprises a second drain coupled to the first drain, a second source coupled to a reverse input terminal and a second gate coupled to the power source. The second PMOS transistor comprises a third gate coupled to the first drain, a third drain coupled to an output terminal and a third source coupled to the power source. The second NMOS transistor comprises a fourth gate coupled to the second gate, a fourth drain coupled to the output terminal and a fourth source coupled to the input terminal.
Moreover, the level shifting circuit of the present invention includes a first PMOS transistor, a voltage difference element, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The first PMOS transistor comprises a first drain, a first gate coupled to an input terminal and a first source coupled to a power source. The voltage difference element includes a first terminal coupled to the first drain, and a second terminal. The second PMOS transistor comprises a second source coupled to the power source, a second gate coupled to the second terminal and a second drain coupled to an output terminal. The first NMOS transistor comprises a third drain coupled to the second gate, a third gate coupled to the first drain and a third source coupled to a reverse input terminal. The second NMOS transistor comprises a fourth source coupled to the input terminal, a fourth drain coupled to the output terminal and a fourth gate coupled to the first drain.